This invention relates to a memory controller for controlling an access to a memory device which is typically a dynamic RAM (random access memory).
Various memory controllers are disclosed in Japanese Unexamined Patent Publications Nos. 61-42793 (42793/1986), 61-98996 (99996/1986), 62-149099 (149099/1987), 1-134544 (134544/1989), 1-158553 (158553/1989). As described in the Publications, either a high-speed page mode or a static column mode is used as a high-speed access mode in accessing a memory device of, for example, a dynamic RAM. Any one of the memory controllers controls the memory device in response to input addresses to access the memory device at the high-speed access mode. Each of the input addresses comprises a row address and a column address.
As will later be described, any one of the memory controllers can not access the memory device at a high speed when supplied with the input addresses with a time interval left between the input addresses having the same row address.